Research Engineer, Chip Design RL (Reinforcement Learning)

Advance AI models' silicon design capabilities using RL and chip design expertise.

• •As a Research Engineer on the Code RL team, you will advance our models' ability to design silicon by leveraging your chip design expertise to create tasks and signals for AI models to learn from.
• •Key Responsibilities Invent, design, and implement RL environments and evaluations for agentic RTL generation, design verification, and physical design optimization.
• •Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
• •Conduct experiments and shape our roadmap.
• •Deliver your work into research and production training runs.
• •Collaborate with other researchers and engineers across and outside Anthropic.
• •Requirements Expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs.
• •Fluent with industry EDA tools and processes.
• •Taped out chips and have experience going from spec to silicon.
• •Know how to balance research exploration with engineering implementation.